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A 0.5 /spl mu/m CMOS 622Mb/s 32/spl times/8 shared-buffer ATM switch chip set consists ofa buffer LSI and a control LSI. It has a 768-cell on-chip buffer controlled by a searchable address queue running at 400 MHz with a double-edge triggered hand-shake circuit. The switch realizes 5 Gb/s total throughput with 8-level delay and 4-level cell-loss priorities for multimedia communications. A funnel structure enables a scalable switch size. 32 bit/frame synchronizers are integrated for all input channels.
Date of Conference: 8-8 Feb. 1997