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A fast parallel squarer based on divide-and-conquer

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3 Author(s)
Yoo, J.-T. ; Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA ; Smith, K.F. ; Gopalakrishnan, G.

Fast and small squarers are needed in many applications such as image compression. A new family of high-performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-μm CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:32 ,  Issue: 6 )