By Topic

A high-speed median circuit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Opris, I.E. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Kovacs, G.T.A.

A high-speed analog median circuit is presented using a two-stage architecture to minimize the errors around the transition corners. Prototypes have been designed and built using the Orbit 2-μm CMOS process. The design has been optimized for low crossover distortion and fast transient recovery in less than 200 ns. The active area is 0.2 mm 2, and the circuit dissipates 7 mW from a single 5 V supply while being able to drive an external 30 pF capacitor

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:32 ,  Issue: 6 )