By Topic

A 1.2 V to 3.3 V wide-voltage-range DRAM with 0.8 V array operation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
M. Tsukude ; ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan ; S. Kuge ; T. Fujino ; K. Arimoto

DRAM arrays operating with power supply below 1 V, with stable sensing and high speed are required for multi-media systems. Reduction of data-retention current is also important. The authors present two data-retention current reduction techniques: charge-transfer pre-sensing scheme (CTPS) with 1/2Vcc bit-line precharge; and non-reset row block control (NRBC). An experimental 32 Mb DRAM using these techniques is fabricated in a 0.25 /spl mu/m triple-well CMOS technology.

Published in:

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Date of Conference:

8-8 Feb. 1997