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Modern CISC and RISC microprocessors use sophisticated caching schemes to bridge the performance mismatch between their internal execution units and the capabilities of commodity memory technologies. A variety of cache architectures and organizations have been developed and are finding use in current and future high-performance computer systems. Designers of systems with next-generation PowerPC/sup TM/ microprocessors face similar challenges. System performance implications for various cache architectures (look-aside, in-line, back-side) and cache organizations (direct-mapped, set-associative) need to be understood so that cost-effective cache hierarchies can be built. This paper presents the results of an analysis done at the Motorola Computer Group to characterize the required properties of a cache hierarchy for a next-generation G3 PowerPC superscalar low-power microprocessor.