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Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

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4 Author(s)
Amerasekera, A. ; Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX ; Mi-Chang Chang ; Duvvury, C. ; Ramaswamy, S.

The design and optimization of ESD protection circuits is greatly enhanced by the ability to perform circuit-level simulations of the protection circuits and the I/O buffers. Most available simulators do not cover the high current region of the circuit operation, but still enable an approximate analysis to be made of the behaviour under ESD conditions. In this article, a description of the behaviour of the MOS device in the high current regime is presented together with the model equations governing that behaviour. The equations have been implemented into a SPICE circuit simulator, and the experimental and simulation results are given. A simple parameter extraction methodology is presented that uses the terminal currents from a single MOS DC I-V curve to obtain all the MOS and bipolar parameters required for the model

Published in:

Circuits and Devices Magazine, IEEE  (Volume:13 ,  Issue: 2 )