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Impact of boron penetration at the p+-poly/gate-oxide interface on the device reliability of deep submicron CMOS logic technology

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3 Author(s)
Nayak, Deepak K. ; Div. of Logic Technol., Adv. Micro Devices Inc., Sunnyvale, CA, USA ; Ming-Yin Hao ; Rakkhit, R.

Impact of boron penetration at the p+-poly/gate-oxide interface is investigated. It is shown that the onset of boron penetration at this interface can not be detected by conventional threshold or flatband voltage shifts of p-channel devices, but it results in significantly lower QBD and Vt instability. Constant current stress in inversion has been found to be most sensitive technique to monitor the onset of boron at the p+-poly/gate-oxide interface

Published in:

Integrated Reliability Workshop, 1996., IEEE International

Date of Conference:

20-23 Oct 1996