By Topic

A test structure for plasma process charging monitor in advanced CMOS technologies

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Kim, S.U. ; Sematech, Austin, TX, USA

In this report, a new plasma damage monitor for advanced CMOS technology with TOX <7 nm is introduced. The proposed damage monitor is very simple, most sensitive to plasma charging, and most of all, correlates to real circuit performance and reliability. The monitor is based on an unconventional antenna structure (a transistor with an isolated gate pad) combined with realistic antenna ratio and the gate oxide leakage measurement only. No other device parameters (Vt, Gm, Idsat, interface states, or QBD) measurements are required. No other antenna design is required. The plasma damage monitor can also be used for future ULSI CMOS manufacturing

Published in:

Integrated Reliability Workshop, 1996., IEEE International

Date of Conference:

20-23 Oct 1996