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Latch-up testing in CMOS IC's

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5 Author(s)
R. Menozzi ; DEIS, Bologna Univ., Italy ; M. Lanzoni ; C. Fiegna ; E. Sangiorgi
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Experimental data obtained by testing CMOS commercial ICs for latchup by means of automatic test equipment are presented. The results unambiguously show that latchup resistance is strongly influenced by interactions among complex structures within the circuit that are overlooked by widely used testing procedures. In particular, it is shown that both multiple pin excitation and static current loading can significantly decrease the component latchup resistance because of effects taking place within the semiconductor as well as through metal lines

Published in:

IEEE Journal of Solid-State Circuits  (Volume:25 ,  Issue: 4 )