By Topic

The implementation of digital echo cancellation in codecs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Friedman, V. ; AT&T Bell Lab., Murray Hill, NJ, USA ; Khoury, J.M. ; Theobald, M. ; Gopal, V.P.

The architecture of a codec in which the echo cancellation is done in two stages, an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter, is presented. The design problems connected with this architecture, such as the signal-to-noise performance of the A/D converter and the limiting effects of the variation of the analog components on the echo cancellation performance of the device and on the structure of the digital balance filters, are discussed. These results were used in the design of a single-power-supply CMOS device implemented in 1.5-μm technology using ΣΔ modulation techniques for A/D and D/A conversion. Its echo cancellation performance is sufficiently high that only one set of coefficients per national standard is necessary

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 4 )