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Synthesis approach to multi-level regular representation for combinational circuits

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2 Author(s)
Chrzanowska-Jeske, M. ; Dept. of Electr. Eng., Portland State Univ., OR, USA ; Chungping Guo

In this paper we present a new approach to the synthesis of regular two-dimensional, multilevel logic arrays. We address a new restricted factorization method to synthesis a combinational function as a two-dimensional multi-level array. This is an integrated logic and layout synthesis method which can be used for full custom design such as module generation or for locally-connected fine-grain FPGAs. We defined a new multi-bus architecture, and developed an algorithm to solve the synthesis problem. The benchmark results show encouraging improvements over previous approaches

Published in:

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on  (Volume:1 )

Date of Conference:

13-16 Oct 1996

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