Cart (Loading....) | Create Account
Close category search window

A fault-tolerant associative memory with high-speed operation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Bergh, H. ; Ericsson Telecom AB, Stockholm, Sweden ; Eneland, J. ; Lundstrom, L.-E.

An 8-kb (128-word×64-b) CMOS associative memory with word and bit-parallel operation is described. The highly parallel and pipelined architecture is optimized for high-speed associative operations. The data processing capability is one word/cycle corresponding to 16 MIPS at a typical cycle time of 60 ns. The memory is fault tolerant under software control. A faulty word location in the memory can be made inaccessible by on-chip circuitry. The device is a complete single-chip associative memory with internally controlled addressing and associative data as output

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 4 )

Date of Publication:

Aug 1990

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.