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Inductance analysis of on-chip interconnects [deep submicron CMOS]

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2 Author(s)
S. Kundu ; Res. Lab., IBM Corp., Austin, TX, USA ; U. Ghoshal

It is generally believed that inductance analysis of on-chip interconnect becomes important when the clock frequency of circuits rises above GHz level. In this paper we show that this perception is not true. It becomes necessary to consider the inductive effects in all circuits implemented in deep submicron CMOS technologies. For 0.25 μm (lithography) technologies, where the supply voltage is expected to be in the range of 1.2-1.8 V, inductive effects are an important consideration regardless of system frequency. Furthermore, contrary to the popular belief we show that inductive effects are important even for highly resistive lines

Published in:

European Design and Test Conference, 1997. ED&TC 97. Proceedings

Date of Conference:

17-20 Mar 1997