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Interface timing verification with delay correlation using constraint logic programming

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2 Author(s)
P. Girodias ; Dept. d''Inf. et de Recherche Oper., Montreal Univ., Que., Canada ; E. Cerny

Using constraint logic programming and relational interval arithmetic, as implemented in CLP (BNR) Prolog, we develop a simple yet complete method for interface timing verification. We show how the problems raised by timing verification (consistency, causality and compatibility) can be formulated as constraint satisfaction problems and solved using relational interval arithmetic when the timing constraints are of the linear, earliest or latest type; we examine the effect of correlation between timing delays (within their specified intervals) and show how an interval delay narrowing method can be applied in this context. The original contribution of this paper is to provide a unifying framework for interface timing verification and to present a method that allows delay correlation to be considered

Published in:

European Design and Test Conference, 1997. ED&TC 97. Proceedings

Date of Conference:

17-20 Mar 1997