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Design of a neural network-based digital multiplier

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2 Author(s)
Biederman, D.C. ; Dept. of Electr. & Comput. Eng., Tennessee Technol. Univ., Cookeville, TN, USA ; Ososanya, E.T.

The successful design of computational systems is often predicated on the realization of fast multiplication in digital or analog hardware. A key design issue is the tradeoff between speed, complexity, and chip area. With this in mind, an innovative fast neural network-based digital multiplier has been designed, trained, and implemented in VLSI using 1 micron double polysilicon CMOS technology. The design is constructed of modules consisting of three basic neural network components: a 2×2 adder, a 2×2 multiplier, and a 3×2-bit adder. The modular approach allows scalability of the multiplier circuit. The neural network circuitry is based on neuMOS transistors. A neuMOS transistor is a metal oxide semiconductor device with several fixed gates (inputs) and a floating gate. The capacitances between the fixed gates and the floating gate constitute the neural network weights. A comparison of speed in terms of gate delays and neuron delays, shows that the neural network-based multiplier was 2 to 3 orders of magnitude faster than the Wallace Tree and ROM-based digital multipliers

Published in:

System Theory, 1997., Proceedings of the Twenty-Ninth Southeastern Symposium on

Date of Conference:

9-11 Mar 1997

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