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PAT: state machine based approach to performance modeling for PowerPCTM microprocessors

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2 Author(s)
Kumar, A. ; Somerset Design Center, Motorola Inc., Austin, TX, USA ; Waldecker, B.

The PAT (Performance Analysis Timer) has been developed and is in use at the Somerset Design Center for the purpose of estimating performance of various processor designs. PAT is a state machine based approach to modeling processor architectures. Each stage in a processor pipeline is represented by a stage in PAT. The flow of instructions through these stages is governed by state machines specified for these stages. This approach allows rapid prototyping of the processor architecture without sacrificing the accuracy of the timer. PAT can be used for rough estimates of performance or detailed performance analysis. The accuracy of a model done using the PAT timer depends on the level of detail included by the modeler

Published in:

Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International

Date of Conference:

5-7 Feb 1997