By Topic

Advanced alterable pipeline timer (adapt): a tool to design a high performance PowerPCTM microprocessor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Burgess, B.G. ; Somerset Design Center, Motorola Inc., Austin, TX, USA ; Plummer Litch, S.

The microprocessor discussed in this paper is a member of the G3 family of PowerPC processors, the third generation of PowerPC microprocessor products. It provides the performance levels required for high end desktop systems while offering the low typical power dissipation and small die size that make it very attractive for portable systems. It is an advanced superscalar design with six execution units, aggressive upstream branch processing, out-of-order instruction execution, and a tightly integrated “backside” L2 cache. Most notably it achieves workstation/server class performance while only dissipating 5 watts. A major portion of the design effort involved architectural performance modeling, making cost/power/performance trade-offs, and verifying performance of the implementation

Published in:

Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International

Date of Conference:

5-7 Feb 1997