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Advanced alterable pipeline timer (adapt): a tool to design a high performance PowerPCTM microprocessor

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2 Author(s)
Burgess, B.G. ; Somerset Design Center, Motorola Inc., Austin, TX, USA ; Plummer Litch, S.

The microprocessor discussed in this paper is a member of the G3 family of PowerPC processors, the third generation of PowerPC microprocessor products. It provides the performance levels required for high end desktop systems while offering the low typical power dissipation and small die size that make it very attractive for portable systems. It is an advanced superscalar design with six execution units, aggressive upstream branch processing, out-of-order instruction execution, and a tightly integrated “backside” L2 cache. Most notably it achieves workstation/server class performance while only dissipating 5 watts. A major portion of the design effort involved architectural performance modeling, making cost/power/performance trade-offs, and verifying performance of the implementation

Published in:

Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International

Date of Conference:

5-7 Feb 1997

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