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Dual basis systolic multipliers for GF(2m)

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3 Author(s)
Fenn, S.T.J. ; Sch. of Eng., Huddersfield Polytech., UK ; Benaissa, M. ; Taylor, O.

Two systolic multipliers for GF(2m) are presented, one bit-serial and one bit-parallel. Both multipliers are hardware efficient and support pipelining. Both architectures are highly regular, require only local communication lines and have longest delay paths independent of m. Consequently these multipliers can be clocked at high speeds and are suitable for VLSI implementation. The design of both these multipliers is also independent of the defining irreducible polynomial for the field

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Computers and Digital Techniques, IEE Proceedings -  (Volume:144 ,  Issue: 1 )