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A reliable hardware barrier synchronization scheme

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3 Author(s)
Rajeev Sivaram ; Dept. of Comput. & Inf. Sci., Ohio State Univ., Columbus, OH, USA ; Stunkel, C.B. ; Panda, D.K.

Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, hardware, or a combination of these mechanisms. However few of these schemes emphasize fault-tolerant barrier operations. In this paper, we describe inexpensive support that can be added to network switches for achieving reliable hardware-based barrier synchronization while recovering from lost or corrupted messages. Necessary modifications to the switch architecture and the associated fault-tolerant message-passing protocols are presented. The protocols are optimized for the no-fault case while providing means to detect the failure of any step of the operation and to recover from it. The proposed scheme shows significant potential for use in parallel systems, especially the emerging systems based on networks of workstations

Published in:

Parallel Processing Symposium, 1997. Proceedings., 11th International

Date of Conference:

1-5 Apr 1997