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Reducing time delay of ARQ protocols by simple error-correcting codes

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2 Author(s)
Yang, Q. ; Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada ; Bhargava, V.K.

Time delay analysis is carried out for type-I hybrid ARQ with BCH codes. It is found that the time delay of ARQ protocols can be significantly reduced by using simple BCH codes. Implementation trade-off can then be made between buffer size and simple decoding facilities to achieve maximum performance and minimum complexity.

Published in:

Electronics Letters  (Volume:26 ,  Issue: 18 )