Referenced Items are not available for this document.
A high-level top-down analog synthesis methodology is presented. It translates an initial signal flow graph representation of a transfer function into an architecture made of interconnected analog primitives. Constraints are imposed on the primitive weights and interconnections to ensure realizability. Transformations that generate realisable architectures are presented and illustrated through examples
Published in:
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Date of Conference: 18-22 Sep 1995
- Page(s):
- 366 - 369
- Meeting Date :
- 18 Sep 1995-22 Sep 1995
- ISSN :
- 1063-0988
- Print ISBN:
- 0-7803-2707-1
- INSPEC Accession Number:
- 5218717
- Conference Location :
- Austin, TX
- Digital Object Identifier :
- 10.1109/ASIC.1995.580750
- Product Type:
- Conference Publications
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