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This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed
Published in:
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Date of Conference: 18-22 Sep 1995
- Page(s):
- 338 - 341
- Meeting Date :
- 18 Sep 1995-22 Sep 1995
- ISSN :
- 1063-0988
- Print ISBN:
- 0-7803-2707-1
- INSPEC Accession Number:
- 5218711
- Conference Location :
- Austin, TX
- Digital Object Identifier :
- 10.1109/ASIC.1995.580744
- Product Type:
- Conference Publications
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