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Single chip array processor for high performance design error simulation

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2 Author(s)
Sungho Kang ; Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea ; Szygenda, S.A.

This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed

Published in:

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Date of Conference:

18-22 Sep 1995

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