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VHDL and silicon compiler experience in the advanced processor interface unit ASIC design

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4 Author(s)
Chang, K.C. ; Boeing Def. & Space Group, Seattle, WA, USA ; Le, H. ; Ling, C. ; Lin, D.

This paper summarizes the process of designing an advanced processor interface unit (APIU) ASIC using VHDL simulation, synthesis, and silicon compilation. Problems and areas for improvements in the interface between different CAD tool environments are addressed. VHDL entity and hierarchy partition guidelines are discussed with examples

Published in:

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Date of Conference:

18-22 Sep 1995