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A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems

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3 Author(s)
Kuo, J.B. ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Lou, J.H. ; Su, K.W.

This paper presents a high-speed 1.5 V clocked BiCMOS dynamic latch, which is derived from a clocked CMOS dynamic latch and a BiCMOS logic gate using BiPMOS pull-down structure, and a bootstrapped pull-up structure, for BiCMOS dynamic pipelined digital logic systems. Based on the study, for driving a load capacitance of 2 pf, the 1.5 V clocked BiCMOS dynamic latch provides a 2.5× improvement in switching time as compared to the clocked CMOS one

Published in:

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Date of Conference:

18-22 Sep 1995