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A single-chip, asynchronous echo canceller for high-speed data communication

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4 Author(s)
Mackey, R.P. ; Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA ; Rodriguez, J.J. ; Carothers, J.D. ; Vrudhula, S.B.K.

A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz

Published in:

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Date of Conference:

18-22 Sep 1995