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A low power based system partitioning and binding technique for multi-chip module architectures

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3 Author(s)
R. V. Cherabuddi ; Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA ; M. A. Bayoumi ; H. Krishnamurthy

In this paper, we present a low power targeted high-level synthesis framework for the synthesis of Multi-Chip Modules (MCM). This new framework is based on minimizing the switching activity on the functional units as well as the inter-chip buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for system partitioning. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs

Published in:

VLSI, 1997. Proceedings. Seventh Great Lakes Symposium on

Date of Conference:

13-15 Mar 1997