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A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths

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4 Author(s)
Wang, L.-Y. ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Lai, Y.-T. ; Liu, B.-D. ; Chang, T.-C.

The layout compaction problem with performance consideration is studied. In our approach, the delay upper-bound on the timing critical paths is reduced first, then the layout size is minimized without increasing that delay bound. Either step is formulated as a linear programming problem, and we propose a graph-based simplex algorithm, which replaces most of the matrix operations with graph operations, to solve the problem. Both theoretical analysis and experimental results show that this algorithm is quite efficient.

Published in:

Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 1993