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Exact evaluation of memory size for multi-dimensional signal processing systems

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3 Author(s)
Balasa, F. ; IMEC, Leuven, Belgium ; Catthoor, F. ; De Man, H.

Memory cost is typically responsible for up to 80% of the chip and/or board area of most video and image processing system realizations. We present a novel technique - founded on data-flow analysis - which allows us to address the problem of background memory size evolution for a given nonprocedural algorithm specification. Usually, the number of signal instances is huge, so a new data-flow model grouping scalar signals in so-called basic sets is proposed. The method also incorporates a way to trade-off memory size with computational and controller complexity.

Published in:

Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 1993