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A new statistical MOS model has been developed for computer-aided design of submicrometer analog integrated circuits. This model accounts for both parameter mismatch and inter-die parameter variations, both of which contribute to statistical variations in analog circuit performance. New characterization methods were developed to improve model fit to parameter standard deviations over a broad range of transistor biases. Implementation of this model in HSPICE is demonstrated, meaning that no exotic simulation tools are required to perform the statistical simulations. The model was tested on a 0.8 /spl mu/m CMOS process, with simulated and measured values of drain current variability showing excellent agreement.