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This paper presents a method of multi-level logic optimization for combinational and synchronous sequential logic. The circuits are optimized through iterative addition and removal of redundancies. Among the large number of possible connections that can be added, the proposed method can efficiently identify those connections that would create more redundancies and, thus, would result in a smaller network. This is done with the use of combinational and sequential ATPG techniques based up the concept of mandatory assignments. Experiments on ISCAS-85 combinational benchmark circuits show that best results are obtained for most of them. For sequential circuits, experimental results on MCNC FSM benchmarks and ISCAS-89 sequential benchmark circuits show that a significant amount of area reduction can be achieved beyond combinational optimization and sequential redundancy removal.