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This paper describes the DEFAM defect to fault mapper, and its use in test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects in the manufacturing process on a design, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the simulation effort needed. It also reports hierarchical faults that can be fed into a hierarchical fault simulator. Yield analysis results are given for designs of up to 164K transistors. Test quality analysis results are given for an adder module.