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Verifying a multiprocessor cache controller using random test generation

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3 Author(s)
Wood, D.A. ; Wisconsin Univ., Madison, WI, USA ; Gibson, G.A. ; Katz, R.H.

The design verification of the cache controller for SPUR, a shared-memory multiprocessor, is reported. The strategy was to develop a random tester that would generate and verify the complex interactions between multiple processors in functional simulation. Replacing the CPU model, the tester generates memory references by random selection from a script of actions and checks. It was easy to develop and detect over half the bugs uncovered during functional simulation. A prototype SPUR multiprocessor system that runs the Sprite operating system is being used for experiments in parallel programming. Results to data are described.<>

Published in:

Design & Test of Computers, IEEE  (Volume:7 ,  Issue: 4 )

Date of Publication:

Aug. 1990

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