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Formal verification of a pipelined microprocessor

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2 Author(s)
Srivas, M. ; Odyssey Res. Associates, Ithaca, NY, USA ; Bickford, M.

The application of modern functional languages and supporting verification technology to a scaled-down but realistic microprocessor is described. The model is of an infinite stream of machine instructions consuming an infinite stream of interrupt signals and is specified at two levels: instruction and hardware design. A correctness criterion is stated for an appropriate sense of equivalent behavior of these levels and proved using a mechanically supported induction argument. The functional-language-based verification system Clio and the Mini Cayuga microprocessor are described. The formal specification and verification process are examined in detail.<>

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Software, IEEE  (Volume:7 ,  Issue: 5 )