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Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation

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7 Author(s)
Nii, K. ; Renesas Electron. Corp., Tokoyo, Japan ; Yabuuchi, M. ; Fujiwara, H. ; Nakano, H.
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We present a fine-grained assist bias control technique for enhancing read-/write-margins of embedded SRAM in deep-submicron SoC. This technique controls the individual assist bias for finely segmented rows and columns of a cell array with small area overheads. We design and fabricate prototype micro-controller test chips with 1 Mb SRAM using 90-nm low-standby-power CMOS technology. The evaluation results demonstrate that Vmin achieves 0.64 V, which is a 21% improvement compared to the conventionally used technique.

Published in:

SOC Conference (SOCC), 2010 IEEE International

Date of Conference:

27-29 Sept. 2010

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