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Exploiting large on-chip memory space through data recomputation

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3 Author(s)

This paper presents a novel on-chip memory space utilization strategy for architectures that accommodate large on-chip software-managed memories. In such architectures, the access latencies of data blocks are typically proportional to the distance between the processor and the requested data. Considering such an on-chip memory hierarchy, we propose to recompute the value of an on-chip data, which is far from the processor, using the closer data elements instead of directly accessing the far data if it is beneficial to do so in terms of performance. This paper presents the details of a compiler algorithm that implements the proposed approach and reports the experimental data collected using six data-intensive applications programs. Our experimental evaluation indicates 8.2% performance improvement, on the average, over a state-of-the-art on-chip memory management strategy and shows consistent improvements for varying on-chip memory sizes and different data access latencies.

Published in:

SOC Conference (SOCC), 2010 IEEE International

Date of Conference:

27-29 Sept. 2010