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A 10B 200MHz pipeline ADC with minimal feedback penalty and 0.35pJ/conversion-step

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4 Author(s)
Gang Chen ; Dept. of Electr. & Comput. Eng., Univ. of New Hampshire, Durham, NH, USA ; Yifei Luo ; Jiayin Tian ; Kuan Zhou

A 200MHz 10-bit pipeline analog-to-digital converter (ADC) that includes a novel multiplying digital-to-analog converter (MDAC) architecture is presented. The proposed MDAC architecture minimizes the feedback penalty, resulting more than 75% power reduction and 50% output noise reduction than those traditional architectures. The proposed MDAC dramatically reduces the settling time and operates much closer to the unity gain frequency of the amplifier. The proposed 10-bit ADC achieves a peak signal-to-noise-and-distortion-ratio (SNDR) of 55.8dB and this SNDR translates to a figure of merit (FOM) of 0.35pJ/conversion-step. To our best knowledge, this is the minimum power consumption ever reported for pipeline ADCs beyond the 200MHz sampling rate and without complex digital calibration. This design has been implemented with the IBM 90nm CMOS technology. The ADC has a 1.2V power supply and 1.2V peak-to-peak differential input signal.

Published in:

SOC Conference (SOCC), 2010 IEEE International

Date of Conference:

27-29 Sept. 2010

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