By Topic

Delay dependent power optimisation of combinational circuits using AND-Inverter graphs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Rashmi Mehrotra ; Dept of Microelectronic Engineering, University College Cork, Ireland ; Tom English ; Emanuel Popovici ; Michel Schellekens

Dynamic power dissipation due to switching activity has been one of the major concerns in power optimisation. By approximating the switching activity of circuit nodes as internal switching probabilities using AND Inverter graphs (AIGs), it is possible to estimate and optimise power dissipation. In our work, the internal switching probabilities are derived via probabilistic estimation method under a variable delay model. Local reordering delay dependent rules are applied on the AIG nodes for the minimisation of overall sum of switching probability. Optimisation techniques such as simulated annealing for conversions from higher switching probability network to lower switching probability network are used in this paper. Combinational circuits used in our work are up to 100k gates and they are implemented using ROM.

Published in:

23rd IEEE International SOC Conference

Date of Conference:

27-29 Sept. 2010