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A CMOS 6 bit 250MS/s A/D converter with input voltage range detectors

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2 Author(s)
Kwang Yoon ; Dept. of EE, Inha Univ., Incheon, South Korea ; Won Kim

This paper proposes a CMOS 6 bit A/D converter with input voltage range detectors based upon folding amplifier with a folded-cascode load. The input voltage range detectors allow the proposed A/D converter to reduce the power dissipation by turning on one fourth of all the comparators. The measurement result illustrates ENOB of 5.1 bits at 250Msps, power dissipation of 106mW, and FoM of 17.5pJ/steps.

Published in:

SOC Conference (SOCC), 2010 IEEE International

Date of Conference:

27-29 Sept. 2010