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A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier

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3 Author(s)
Jiaping Hu ; Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA ; Yong-Bin Kim ; Ayers, J.

In this paper, the design, implementation and simulation of a high-transimpedance gain, ultra low-power dissipation and low-noise CMOS front-end transimpedance amplifier (TIA) is presented. For interfacing with bio-sensor array and analog neuron circuit, an improved capacitive-feedback TIA topology is adopted with active load to obtain a 131 M gain, 1.45 MHz bandwidth, 90.8fA/rt(Hz) input-referred current noise at the sampling frequency, less than 1° phase response at the sampling frequency, and 520 mV peak-to-peak output swing. The proposed circuit dissipates less than 30 μW with 0.8 V supply voltage, and the circuit is implemented in 65 nm CMOS Predictive Technology Model.

Published in:

SOC Conference (SOCC), 2010 IEEE International

Date of Conference:

27-29 Sept. 2010

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