Analysis of Edge Wordline Disturb in multimegabit charge trapping flash NAND arrays

The Edge Wordline Disturb (EWD) represented a reliability issue on traditional Flash NAND memories, evidenced as an unwanted positive threshold voltage shift of all the cells belonging to the first wordline (WL0) connected to the Ground Select Transistor (GSL). In this work, throughout the experimental characterization of Multimegabit arrays it has been investigated the presence and the physical nature of the EWD in Charge Trapping (CT) NAND Flash, emphasizing its dependency on parameters such as the programming voltage, the inhibit voltage and device aging.