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With scaling down of device geometry and keeping improvement of the chip resistance capacitance (RC) delay, it is necessary to reduce k value. A porous ultra low k-value (ULK) dielectric film is integrated into Cu interconnects of advanced 40 nm. There are several papers discussing about the interface effect between ULK film and barrier on reliability performance. This paper will discuss the effect of pre-clean process on reliability performance before barrier and Cu-seed layer deposition that will strong affect the interface properties. Also, the early failure mode of each pre-clean process will be discussed as well to clarify the proposed mechanism.