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A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm ^{2} 65 nm CMOS Circuit

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3 Author(s)
Enrique Prefasi ; Electronics Technology Dept., Carlos III University, Madrid, Spain ; Susana Paton ; Luis Hernandez

This work presents an area- and power-efficient realization of a new time-encoding oversampling converter (TEOC) consisting of a third-order continuous time (CT) loop filter and a self-oscillating pulse-width modulator (PWM). The modulator displays similar performance to that of a standard multibit CT-ΣΔ modulator but has the complexity of a single bit design. The time-encoding quantizer (TEQ) is implemented inside a ΣΔ modulator by replacing a multibit quantizer. An innovative TEQ is used to overcome design issues in a 1.0 V supply-voltage 65 nm digital CMOS technology. The TEQ allows an exchange of amplitude-resolution by time-resolution. The approach of time-resolution alleviates the scaling difficulties of mixed-signal circuits in nano-scale technologies. The TEOC features a 63 dB dynamic-range and a peak-SNDR of 61 dB over a 20 MHz signal bandwidth. Clocked at 2.5 GHz, the complete ADC consumes 7 mW from a single 1.0 V supply, including also the reference buffers. The ADC core results in an attractively small area of 0.08 mm2 and in a figure-of-merit (FoM=Pwr/2 · BW · 2ENOB) of 0.17 pJ/conversion-step.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:46 ,  Issue: 7 )