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Design and analysis of tree-multiplier using single-clocked energy efficient adiabatic Logic

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5 Author(s)
Chanda, M. ; BESU, VLSI Technol. Lab., Howrah, India ; Kundu, S. ; Adak, I. ; Dandapat, A.
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In this paper ultra low power characteristics of the newly proposed energy efficient adiabatic Logic (EEAL) is investigated. EEAL is based on differential cascode voltage swing (DCVS) logic, uses only a single sinusoidal source as supply-clock. With minimal clocking overhead this proposed logic eliminates the floating output problem and enhances the energy efficiency significantly. An EEAL based 8×8 tree multiplier by 4-2 compressor circuits have been implemented in a TSMC 0.18 μm CMOS technology. CADENCE simulation shows that EEAL based multiplier circuit consumes only 25%-30% of total energy consumed by single clocked adiabatic logics. Both simulation and measurement results verify the functionality of such logic, making it suitable for implementing energy-aware and performance-efficient sequential circuit.

Published in:

Students' Technology Symposium (TechSym), 2011 IEEE

Date of Conference:

14-16 Jan. 2011