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Enhancing online error detection through area-efficient multi-site implications

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5 Author(s)
Alves, N. ; Sch. of Eng., Brown Univ., Providence, RI, USA ; Shi, Y. ; Dworak, J. ; Bahar, R.I.
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We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic.

Published in:

VLSI Test Symposium (VTS), 2011 IEEE 29th

Date of Conference:

1-5 May 2011