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In this paper, we propose an ultra high-throughput LDPC decoder SOC to fulfill the requirement of IEEE 802.15.3c standard. By implementing a macro-layer fully parallel architecture, our proposed decoder takes only 4 clock cycles to finish one layered decoding iteration. Interconnection complexity problem introduced by high-parallel decoding is nicely solved by proposed reusable message permutation networks utilizing the features of code PCM. Critical path is shortened by applying frame-level pipeline decoding. A 65 nm CMOS chip is fabricated to verify the proposed architecture. Measured at 1.2 V, 400 MHz and 10 iterations the proposed decoder achieves a data throughput 6.72 Gb/s and consumes a power 537.6 mW with an energy efficiency 8.0 pJ/bit·iter.
Date of Conference: 25-28 April 2011