Skip to Main Content
This paper discusses the implementation details and silicon result of a 1.6 GHz dual-core Cortex-A9 on a low power High-K Metal Gate 32 nm CMOS Bulk Process. The implementation is based on a fully synthesizable flow utilizing ARM Standard Cell and Memory IP. The completed design includes power gating and Dynamic Voltage Frequency Scaling capabilities for low static and dynamic power consumption and achieves beyond GHz+ nominal operating frequency. This paper will outline the chip architecture, discuss the implementation and challenges encountered during design and present results measured from the functional silicon.