By Topic

A V-band CMOS sub-harmonic mixer with integrated frequency doubler and 180°out-of-phase splitter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chi-Chen Chen ; Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, ROC ; Yo-Sheng Lin ; Jen-How Lee ; Jin-Fa Chang

A V-band sub-harmonic mixer with an integrated frequency doubler and a 180o out-of-phase splitter using standard 0.13 μm CMOS technology is reported. The sub-harmonic mixer comprises a current-reused bleeding mixer, a baseband amplifier, a 180° (Wilkinson-power-divider-based) out-of-phase splitter, and a frequency doubler. The mixer consumed 31.5 mW and achieved input return loss at RF port better than -10 dB for frequencies from 49.8 GHz to 63 GHz. At IF of 20 MHz, the mixer achieved maximum conversion gain of 9.5 dB at RF of 53 GHz. The corresponding 3-dB bandwidth (ω3db) of RF is 9.6 GHz (48.4 ~ 58 GHz). The measured LO-to-RF and LO-to-IF isolation were better than -50 dB over the frequency band of interest. In addition, the measured input 1-dB compression point (P1dB) and input third-order inter-modulation point (IIP3) were -8 dBm and 2.2 dBm, respectively, at RF of 60 GHz. These results demonstrate the proposed mixer architecture is very promising for high- performance V-band RFIC applications.

Published in:

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Date of Conference:

25-28 April 2011