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High performance DDR architecture in Intel® Core™ processors using 32nm CMOS high-K metal-gate process

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3 Author(s)
Praveen Mosalikanti ; Intel Corporation, 2111 NE 25 Ave, Hillsboro, OR 97124 USA ; Chris Mozak ; Nasser Kurd

This paper describes the DDR architecture in Intel® Core™ processors operating up to 1333MT/s and designed in 32nm process technology. The architecture uses adaptive techniques to achieve very low clock jitter (40% margin to spec), data scrambling to reduce simultaneous switching noise and novel training algorithms to improve I/O margins in the presence of crosstalk. A fast wakeup technique allows shutting down the receive path for finer grain power management, reducing standby power by 15%.

Published in:

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Date of Conference:

25-28 April 2011