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A 1-V 8-bit 100kS/s-to-4MS/s asynchronous SAR ADC with 46fJ/conv.-step

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4 Author(s)
Yen-Ju Chen ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Jen-Huan Tsai ; Meng-Hung Shen ; Po-Chiun Huang

This paper presents a low-power speed-scalable 8bit Successive Approximation Register (SAR) ADC implemented in 0.18-μm CMOS. By designing a compact asynchronous controller and a charge-sharing DAC, the power consumption can be linearly scaled with the conversion speed. A maximum power dissipation of 28.4 μW and 0.019 mm2 total area make this ADC ideal for highly integrated wireless sensor nodes. The measured ENOB at Nyquist frequency at 4 MS/s is 7.3 bit, corresponding to a general FoM of 46 fJ/conv.-step. The embedded asynchronous controller allows the ADC to achieve the same energy efficiency over a wide conversion speed from 100 kS/s to 4 MS/s.

Published in:

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Date of Conference:

25-28 April 2011

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